This application claims the priority benefit of Taiwan application serial no. 91104343, filed Mar. 8, 2002.
1. Field of Invention
The present invention relates to a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a non-volatile memory (NVM) and the fabrication thereof.
2. Description of Related Art
The family of the non-volatile memory includes the substrate/oxide/nitride/oxide/silicon (SONOS) memory. The structure of a conventional SONOS non-volatile memory is schematically illustrated in FIG. 1 in a cross-sectional view.
Refer to FIG. 1, the SONOS memory comprises a substrate 100, a word-line 112 on the substrate 100, an oxide/nitride/oxide (ONO) layer 104 as a charge trapping layer between the substrate 100 and the word-line 112, a buried bit-line 108 in the substrate 100 beside the ONO layer 104, and a buried bit-line oxide layer 110 between the buried bit line 108 and the word line 112. A channel region (not shown) is thus defined in the substrate 100 under the charge trapping layer 104.
Since the channel region in a conventional SONOS non-volatile memory is flat, the channel width decreases as the memory cell is scaled down and the channel current is thus decreased. Therefore, the difference between the xe2x80x9cOnxe2x80x9d current and the xe2x80x9cOffxe2x80x9d current, which is equal to the difference between the channel current at the logic state xe2x80x9c0xe2x80x9d and the channel current at the logic state xe2x80x9c1xe2x80x9d, is decreased and data-reading errors easily occurs.
Accordingly, this invention provides a non-volatile memory and the fabrication thereof to avoid the channel current from being decreased when the memory cell is scaled down, or to increase the channel current in a memory cell of the same size.
This invention also provides a non-volatile memory and the fabrication thereof to provide a sufficient difference in the channel current between the xe2x80x9c0xe2x80x9d state and the xe2x80x9c1xe2x80x9d state when the memory cell is miniaturized, or to increase the difference between the xe2x80x9c0xe2x80x9d state and the xe2x80x9c1xe2x80x9d state in a memory cell of the same size.
The non-volatile memory of this invention comprises a substrate having a trench therein, a buried bit-line crossing the trench, a word-line covering at least the trench and crossing over the buried bit-line, and a charge trapping layer between the substrate and the word-line. Moreover, a buried bit-line oxide layer is disposed between the buried bit-line and the word-line.
The fabrication of the non-volatile memory of this invention comprises the following steps. A trench, such as a U-shaped trench, is formed in a substrate and then a charge trapping layer is formed on the substrate and on the trench. A lithography process and an etching process are performed to expose a strip region of the substrate crossing the trench. A buried bit-line is formed in the substrate within the region and then a buried bit-line oxide layer is formed on the buried bit-line. Subsequently, a word-line is formed covering the trench and crossing over the buried bit-line.
Since the word-line extends along the trench and crosses over the buried bit-line in the non-volatile memory of this invention, the channel has a curved cross section and the effective channel width is thus increased. Therefore, the channel current is increased and the difference between the xe2x80x9c0xe2x80x9d state and the xe2x80x9c1xe2x80x9d state or between the xe2x80x9cOnxe2x80x9d current and the xe2x80x9cOffxe2x80x9d current is larger.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.